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EM78P156E
I.
GENERAL DESCRIPTION
EM78P156E is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 1K*13bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent a user's code from intruding as well as 7 OPTION bits to match the user's requirements. Because of the OTP-ROM, the EM78P156E offers users a convenient way to develop and verify their programs. Moreover, a user's developed code can be programmed easily by an EMC writer.
II.
FEATURES
* * * * Operating voltage range: 2.2V~5.5V Available in temperature range: 0C~70C Operating frequency range: DC ~ 36MHz Low power consumption: * less than 1.6 mA at 5V/4MHz * typical of 15 A at 3V/32KHz * typical of 1 A during the sleep mode 1Kx13 bits on chip ROM One security register to prevent the code in the OTP memory from intruding One configuration register to match the user's requirements 48x8 bits on chip registers (SRAM) 2 bi-directional I/O ports 5 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Two clocks per instruction cycle Power-down mode (SLEEP mode) Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt Programmable free running watchdog timer 8 pull-high pins 7 pull-down pins 8 open-drain pins Two R-option pins Package type: SOP, SOIC and DIP 99.9% single instruction cycle commands
* * * * * * * * * *
* * * * * * *
* This specification is subject to be changed without notice.
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III. PIN ASSIGNMENTS
EM78P156E
P52 P53 TCC RESET VSS P60,INT P61 P62 P63 1 2 3 4 5 6 7 8 9 DIP SOP SOIC 18 17 16 15 14 13 12 11 10 P51 P50 OSCI OSCO VDD P67 P66 P65 P64
Fig. 1 Pin assignments
IV. FUNCTIONAL BLOCK DIAGRAM
OSCI OSCO /RESET TCC
Oscillator/Timing Control WDT Timer
/INT
R2
Prescaler
Stack
ROM
Internal C External R oscillator WDT Time-out
IOCA
R1(TCC)
Interrupt Controller
Instruction register
ALU
RAM
Instruction Decoder
Sleep & Wake Control
R3
R4
ACC
DATA & CONTROL BUS
IOC5 R5
IOC6 R6
P 5 0
P 5 1
P 5 2
P 5 3
PPPPPPPP 66666666 01234567
Fig. 2 Functional block diagram
V.
PIN DESCRIPTION
Symbol I/O I Function * XTAL type : Crystal input terminal or external clock input pin. * ERC type: RC oscillator input pin. * IRC type: 50K ohm pulled high for 4MHz. * XTAL type: Output terminal for crystal oscillator or external clock input pin. * RC type: Instruction clock ouput. * External clock signal input. * Real time clock/counter with Schmitt trigger input pin, must be tied to VDD or VSS if not in use.
Table 1 Pin description-EM78P156E
OSCI
OSCO
I/O
TCC
I
* This specification is subject to be changed without notice.
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Symbol /RESET P50~P53 P60~P67
I/O I I/O I/O
Function * Input pin with Schmitt trigger. If this pin remains at logic low, the controller will keep in reset condition. * P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50~P52 can be pulled down by software . * P60~P67 are bi-directional I/O pins. These can be pull-high or can be opendrain by software programming. In addition, P60~P63 can be pull-down also by software. * External interrupt pin triggered by falling edge. * Power supply. * Ground.
/INT VDD VSS
I -
VI. FUNCTION DESCRIPTION
VI.1 Operational Registers 1. R0 (Indirect Addressing Register) * R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 2. R1 (Time Clock /Counter) * Increased by an external signal edge which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. * Writable and readable as any other registers. 3. R2 (Program Counter) & Stack * R2 and hardware stacks are 10~12-bit wide. The structure is depicted in Fig. 3. * Generating 1024x13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. * The contents of R2 are set all "0"s upon a RESET condition. * "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. * "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can locate anywhere within a page. " RET" ("RETL K", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2,A" allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared. * "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. * Any instruction which would change the contents of R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",......) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. * All instructions are single instruction cycle (fclk/2) except the instructions which would change the contents of R2 need one more instruction cycle.
* This specification is subject to be changed without notice.
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CALL
PC
A11 A10
A9 A8
A7 ~ A0
RET RETI RETL
000
00
PAGE 0
3FF
Stack 1 Stack 2 Stack 3 Stack 4 Stack 5
Fig. 3 Program counter organization
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 R1(TCC) R2(PC) R3(Status) R4(RSR) R5(Port5) R6(Port6)
Stack (5 levels)
IOC5 IOC6
RF R10 : : 48x8 Common Register
IOCA IOCB IOCC IOCD IOCE IOCF
: :
3F
R3F
Fig. 4 Data memory configuration
* This specification is subject to be changed without notice.
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4. R3 (Status Register) 7 GP2 * * * * Bit 0 (C) Bit 1 (DC) Bit 2 (Z) Bit 3 (P) 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C
* Bit 4 (T) * Bit 5~7 (GP0~2) 5.
Carry flag Auxiliary carry flag Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Power-down bit. Set to 1 during power-on or by a "WDTC" command and reset to 0 by a "SLEP" command. Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during power-up and reset to 0 by WDT time-out. General-purpose read/write bits.
R4 (RAM Select Register) * Bits 0 ~ 5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode. * Bits 6 ~ 7 are general-purpose read/write bits. * See the configuration of the data memory in Fig.4.
6.
R5 ~ R6 (Port 5 ~ Port 6) * R5 and R6 are I/O registers. * Only the lower 4 bits of R5 are available.
7.
RF (Interrupt Status Register) 7 * * * * * * * * 6 5 4 3 2 EXIF 1 ICIF 0 TCIF
"1" means interrupt request, and "0" means non-interrupt occurence. Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC timer overflows, reset by software. Bit 1 (ICIF) Port 6 input status changed interrupt flag. Set when Port 6 input changes, reset by software. Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. Bits 3 ~ 7 Not used. RF can be cleared by instruction but can not be set. IOCF is the interrupt mask register. Note that the result of reading RF is the "logic AND" of RF and IOCF.
8.
R10 ~ R3F * All of these are the 8-bit general-purpose registers.
VI.2 Special Purpose Registers 1. A (Accumulator)
* This specification is subject to be changed without notice.
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* Internal data transfer, or instruction operand holding * It can not be addressed. 2. CONT (Control Register) 7 6 /INT 5 TS 4 TE 3 PAB 2 PSR2 1 PSR1 0 PSR0
Bit 0 (PSR0)~Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT Bit 4 (TE) TCC signal edge 0: increment if the transition from high to low takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: transition on TCC pin Bit 6 (INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instruction * CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) * "1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. * Only the lower 4 bits of IOC5 are able to be defined. * IOC5 and IOC6 registers are both readable and writable. 4. IOCA (Prescaler Counter Register) * IOCA register is readable. * The value of IOCA is equal to the contents of Prescaler counter. * Down counter.
* This specification is subject to be changed without notice.
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5. IOCB (Pull-down Control Register) 7 /PD7 6 /PD6 5 /PD5 4 /PD4 3 2 /PD2 1 /PD1 0 /PD0
Bit 0 (/PD0) Control bit used to enable the pull-down of P50 pin. 0: Enable internal pull-down 1: Disable internal pull-down Bit 1 (/PD1) Control bit used to enable the pull-down of P51 pin. Bit 2 (/PD2) Control bit used to enable the pull-down of P52 pin. Bit 3 Not used. Bit 4 (/PD4) Control bit used to enable the pull-down of P60 pin. Bit 5 (/PD5) Control bit used to enable the pull-down of P61 pin. Bit 6 (/PD6) Control bit used to enable the pull-down of P62 pin. Bit 7 (/PD7) Control bit used to enable the pull-down of P63 pin. * IOCB register is both readable and writable. 6. IOCC (Open-drain Control Register) 7 OD7 6 OD6 5 OD5 4 OD4 3 OD3 2 OD2 1 OD1 0 OD0
Bit 0 (OD0) Control bit used to enable the open-drain of P60 pin. 0: Disable open-drain output 1: Enable open-drain output Bit 1 (OD1) Control bit used to enable the open-drain of P61 pin. Bit 2 (OD2) Control bit used to enable the open-drain of P62 pin. Bit 3 (OD3) Control bit used to enable the open-drain of P63 pin. Bit 4 (OD4) Control bit used to enable the open-drain of P64 pin. Bit 5 (OD5) Control bit used to enable the open-drain of P65 pin. Bit 6 (OD6) Control bit used to enable the open-drain of P66 pin. Bit 7 (OD7) Control bit used to enable the open-drain of P67 pin. * IOCC register is both readable and writable. 7. IOCD (Pull-high Control Register) 7 /PH7 6 /PH6 5 /PH5 4 /PH4 3 /PH3 2 /PH2 1 /PH1 0 /PH0
Bit 0 (/PH0) Control bit used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable internal pull-high Bit 1 (/PH1) Control bit used to enable the pull-high of P61 pin. Bit 2 (/PH2) Control bit used to enable the pull-high of P62 pin. Bit 3 (/PH3) Control bit used to enable the pull-high of P63 pin. Bit 4 (/PH4) Control bit used to enable the pull-high of P64 pin. Bit 5 (/PH5) Control bit used to enable the pull-high of P65 pin.
* This specification is subject to be changed without notice.
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Bit 6 (/PH6) Control bit used to enable the pull-high of P66 pin. Bit 7 (/PH7) Control bit used to enable the pull-high of P67 pin. * IOCD register is readable and writable. 8. IOCE (WDT Control Register) 7 WDTE 6 EIS 5 4 ROC 3 2 1 0 -
Bit 7 (WDTE) Control bit used to enable Watchdog Timer. 0: Disable WDT. 1: Enable WDT. * WDTE is both readable and writable. Bit 6 (EIS) Control bit used to define the function of P60 (/INT) pin. 0: P60, bi-directional I/O pin. 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1". * When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig.7(a). * EIS is both readable and writable. Bit 4 (ROC) ROC is used for the R-option. Setting the ROC to "1" will enable the status of R-option pins (P50~P51) to be read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, the user must connect the P51 pin or/and P50 pin to VSS by a 430K external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) will be read as "0"/"1". Refer to Fig.8. * ROC is readable and writable. Bits 0~3, 5 Not used. 9. IOCF (Interrupt Mask Register) 7 6 5 4 3 2 EXIE 1 ICIE 0 TCIE
Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt Bits 3~7 Not used. * Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". * Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.10. * IOCF register is both readable and writable.
* This specification is subject to be changed without notice.
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VI.3 TCC/WDT & Prescaler There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or the WDT only at the same time and the PAB bit of the CONT register is used to determine the prescaler assigment. The PSR0~PSR2 bits determine the ratio. The prescaler will be cleared by the instructions which write to TCC each time, when assigned to TCC mode. The WDT and prescaler, when assigned to WDT mode, will be cleared by the "WDTC" and "SLEP" instructions. Fig.5 depicts the circuit diagram of TCC/WDT. * R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 in every instruction cycle (without prescaler). Refer to Fig.5, CLK=Fosc/2 or CLK=Fosc/4 is depended on the CODE option bit CLKS. CLK=Fosc/2 if CLKS bit is "0", and CLK=Fosc/4 if CLKS bit is "1". If TCC signal source is from external clock input, TCC will increase by 1 on every falling edge or rising edge of TCC pin. * The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even the oscillator driver has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode by software programming. Refer to WDTE bit of IOCE register. With no presacler, the WDT time-out period is approximately 18 ms.
CLK(Fosc/2 or Fosc/4)
0
Data Bus
1
TCC Pin
1
M U X
0
M U X
SYNC 2 cycles
TCC(R1)
TE
TS
PAB
TCC overflow interrupt
0
WDT
1
M U X
8-bit Counter
IOCA
PSR0 ~PSR2 PAB WDTE (in IOCE)
8-to-1 MUX
0 1
MUX
PAB
WDT time-out
Fig. 5 Block diagram of TCC and WDT VI.4 I/O Ports The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also have open-drain output by software. There is an input status changed interrupt (or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control registers (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to 1. While the R-option function is used, P50~P51 are recommended to be used as output pins. During the period of R-option being enabled, P50~P51 must be programmed as input pins. In the R-option mode, the current consuming by the Rex should be taken into the consideration, if the low power consumption is concerned.
* This specification is subject to be changed without notice.
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The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in Fig.6 and Fig.7(a), 7(b) respectively.
PCRD
Q Q
P D R CLK C L
PCWR
PORT
Q Q
P D R CLK C L
IOD
PDWR PDRD
0 1
M U X
*Pull-down is not shown in the figure. Fig. 6 The circuit of I/O port and I/O control register for Port 5
PCRD
QPD R CLK QC L PCWR
P60, /INT PORT P QR D CLK QC L Bit 6 of IOCE 0 1
IOD
PDWR
D PQ R
CLK CQ L
M U X
TI0 PDRD
DRQ
CLK C LQ INT
P
*Pull-high (down) and open-drain are not shown in the figure. Fig. 7(a) The circuit of I/O port and I/O control register for P60(/INT)
* This specification is subject to be changed without notice.
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PCRD
QPD R CLK QC L PCWR
P61~P67 PORT QP D R CLK QC L 0 1
IOD
PDWR
M U X
TIn PDRD
DRQ
CLK C LQ
P
*Pull-high (down) and open-drain are not shown in the figure.
Fig. 7(b) The circuit of I/O port and I/O control register for P61~P67
IOCF.1
P DR Q
Interrupt
CLK CQ L
VCC
TI0 TI1
RF.1
ENI instruction
P DR Q CLK CQ L P QRD CLK QC L
DISI instruction
TI7
/SLEP
Interrupt (Wake-up from SLEEP)
Next Instruction (Wake-up from SLEEP)
Fig. 7(c) Block diagram of I/O Port 6 with input changed interrupt/wake-up
* This specification is subject to be changed without notice.
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EM78P156E
Table 2 Usage of Port 6 input changed wake-up/interrupt function Usage of Port 6 Input Status Changed Wake-up/Interrupt (I) Wake-up from Port 6 input status changed (II) Port 6 input status changed Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT1 (using very carefully) 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1) 3. Execute "ENI" or "DISI" 4. If Port 6 changed (interrupt) 4. Enable interrupt (Set IOCF.1) Interrupt vector (008H) 5. Execute "SLEP" instruction (b) After wake-up 1. If "ENI" Interrupt vector (008H) 2. If "DISI" Next instruction
1
Note : Software disables WDT (watchdog timer) but hardware must be enabled before using port6 changed wake-up function. (CODE Option Register, bit 11 (ENWDTB-) set to "1").
VCC ROC Weekly Pull-up
Q PD R CLK QC L PCWR
PCRD
PORT
Q Q
PD R CLK C L
IOD PDWR
Rex *
0 1
M U X
PDRD
* The Rex is 430K ohm external resistor.
Fig. 8 The circuit of I/O port with R-option (P50,P51) VI.5 RESET and Wake-up 1. RESET The RESET can be caused by (1) Power-on reset (2) /RESET pin input "low", or (3) WDT time-out (if enabled). Note that only power-on reset, or only voltage detector in Case (1) is enabled in the system by CODE option bit. Refer to Fig. 9. The device will be kept in a RESET condition for a period of approx. 18ms (one-oscillator startup timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * All I/O port pins are configured as input mode (high-impedance state).
* This specification is subject to be changed without notice.
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* * * * * * * * * The Watchdog Timer and prescaler are cleared. Upon power-on, the upper 3 bits of R3 are cleared. The bits of the CONT register are set to all "1" except the bit 6 (INT flag). The bits of the IOCA register are set to all "1". The bits of the IOCB register are set to all "1". The IOCC register is cleared. The bits of the IOCD register are set to all "1". Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared. Bits 0~2 of RF register and bits 0~2 of IOCF register are cleared.
Executing the "SLEP" instruction can perform the sleep mode (power-down mode). While entering sleep mode, WDT (if enabled) is cleared but keeps running. The controller can be awakened by (1) external reset input on /RESET pin, (2) WDT time-out (if enabled), or (3) Port 6 input status changed (if enabled). The first two cases will cause the EM78P156E to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wakeup. If DISI is executed before SLEP, the instruction will restart from the place where is right next to SLEP after wake-up. Only one of the cases 2 and 3 can be enabled before entering the sleep mode. That is, [a] if Port 6 input status changed interrupt is enabled before SLEP , WDT must be disabled by software; however, the WDT bit in the option register is still enabled. Hence, the EM78P156E can be awakened only by case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 input status changed interrupt must be disabled. Hence, the EM78P156E can be awakened only by case 1 or 2. Refer to the section on interrupt. If Port 6 input status changed interrupt is used to wake up the EM78P156E (the case [a]), the following instructions must be executed before SLEP: MOV A, 0bxx000110 CONTW CLR R1 MOV A, 0bxxxx1110 CONTW WDTC MOV A, 0b0xxxxxxx IOW RE MOV R6, R6 MOV A, 0b00000x1x IOW RF ENI (or DISI) SLEP ; Sleep NOP ; Select internal TCC clock ; Clear TCC and prescaler ; Select WDT prescaler ; Clear WDT and prescaler ; Disable WDT ; Read Port 6 ; Enable Port 6 input changed interrupt ; Enable (or disable) global interrupt
One problem should be aware that after waking up from the sleep mode, WDT would enable automatically. The WDT operation (being enabled or disabled) should be handled appropriately by software after waking up from the sleep mode.
* This specification is subject to be changed without notice.
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Table 3 The summary of the initialized values for registers Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name X X X X C53 N/A IOC5 Power-on U U U U 1 /RESET and WDT U U U U 1 Wake-up from Pin Changed U U U U P Bit Name C67 C66 C65 C64 C63 N/A IOC6 Power-on 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 Wake-up from Pin Changed P P P P P Bit Name X /INT TS TE PAB N/A CONT Power-on 1 0 1 1 1 /RESET and WDT 1 0 1 1 1 Wake-up from Pin Changed P P P P P Bit Name 0X00 R0(IAR) Power-on U U U U U /RESET and WDT P P P P P Wake-up from Pin Changed P P P P P Bit Name 0X01 R1(TCC) Power-on 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 Wake-up from Pin Changed P P P P P Bit Name 0X02 R2(PC) Power-on 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 Wake-up from Pin Changed **0/P **0/P **0/P **0/P **1/P Bit Name GP2 GP1 GP0 T P 0X03 R3(SR) Power-on 0 0 0 1 1 /RESET and WDT 0 0 0 T T Wake-up from Pin Changed P P P T T Bit Name GP1 GP0 0x04 R4(RSR) Power-on 1 1 U U U /RESET and WDT 1 1 P P P Wake-up from Pin Changed 1 1 P P P Bit Name X X X X P53 0x05 R5(P5) Power-on 0 0 0 0 U /RESET and WDT 0 0 0 0 P Wake-up from Pin Changed 0 0 0 0 P Bit Name P67 P66 P65 P64 P63 0x06 R6(P6) Power-on U U U U U /RESET and WDT P P P P P Wake-up from Pin Changed P P P P P Bit Name X X X X X 0x0F RF(ISR) Power-on U U U U U /RESET and WDT U U U U U Wake-up from Pin Changed U U U U U Bit Name 0x0A IOCA Power-on 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 Wake-up from Pin Changed P P P P P
Bit 2 C52 1 1 P C62 1 1 P PSR2 1 1 P U P P 0 0 P 0 0 **0/P Z U P P U P P P52 U P P P62 U P P EXIF 0 0 P 1 1 P
Bit 1 C51 1 1 P C61 1 1 P PSR1 1 1 P U P P 0 0 P 0 0 **0/P DC U P P U P P P51 U P P P61 U P P ICIF 0 0 P 1 1 P
Bit 0 C50 1 1 P C60 1 1 P PSR0 1 1 P U P P 0 0 P 0 0 **0/P C U P P U P P P50 U P P P60 U P P TCIF 0 0 P 1 1 P
* This specification is subject to be changed without notice.
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Address 0x0B Name IOCB Reset Type Bit 7 Bit Name /PD7 Power-on 1 /RESET and WDT 1 Wake-up from Pin Changed P Bit Name OD7 Power-on 0 /RESET and WDT 0 Wake-up from Pin Changed P Bit Name /PH7 Power-on 1 /RESET and WDT 1 Wake-up from Pin Changed P Bit Name WDTC Power-on 1 /RESET and WDT 1 Wake-up from Pin Changed 1 Bit Name X Power-on U /RESET and WDT U Wake-up from Pin Changed U Bit Name Power-on U /RESET and WDT P Wake-up from Pin Changed P Bit 6 /PD6 1 1 P OD6 0 0 P /PH6 1 1 P EIS 0 0 P X U U U U P P Bit 5 /PD5 1 1 P OD5 0 0 P /PH5 1 1 P X U U U X U U U U P P Bit 4 /PD4 1 1 P OD4 0 0 P /PH4 1 1 P ROC 0 0 P X U U U U P P Bit 3 X U U U OD3 0 0 P /PH3 1 1 P X U U U X U U U U P P Bit 2 /PD2 1 1 P OD2 0 0 P /PH2 1 1 P X U U U EXIE 0 0 P U P P Bit 1 /PD1 1 1 P OD1 0 0 P /PH1 1 1 P X U U U ICIE 0 0 P U P P Bit 0 /PD0 1 1 P OD0 0 0 P /PH0 1 1 P X U U U TCIE 0 0 P U P P
0x0C
IOCC
0x0D
IOCD
0x0E
IOCE
0x0F
IOCF
0x10 ~ 0x3F
R10~R3F
** To jump address 0x08, or to execute the instruction which is next to the "SLEP" instruction. X: not used. U: unknown or don't care. P: previous value before reset. t: check Table 4 2. The status of T and P of STATUS register A RESET condition can be caused by the following events: 1. a power-on condition, 2. a high-low-high pulse on /RESET pin, and 3. Watchdog Timer time-out. The values of T and P, listed in Table 4 can be used to check how the processor wakes up. Table 5 shows the events which may affect the status of T and P . Table 4 The values of T and P after RESET Reset Type Power-on /RESET during operating mode /RESET wake-up during SLEEP mode WDT during operating mode WDT wake-up during SLEEP mode Wake-up on pin changed during SLEEP mode *P: Previous status before reset
T 1 *P 1 0 0 1
P 1 *P 0 P 0 0
* This specification is subject to be changed without notice.
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EM78P156E
Table 5 The status of T and P being affected by events Event Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during SLEEP mode *P: Previous value before reset
T 1 1 0 1 1
P 1 1 *P 0 0
VDD Oscillator DQ CLK CLR 1 M U X
CLK
Power-on Reset Voltage Detector CODE Option WDTE
0
/Enable
WDT Timeout WDT /RESET
18 ms
RESET
Fig. 9 Block diagram of Reset of controller VI.6 Interrupt EM78P156E has three falling edge interrupts listed below : (1) TCC overflow interrupt (2) Port 6 input status changed interrupt (3) External interrupt [(P60//INT) pin]. Before Port 6 input status changed interrupt being enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary. Each pin of Port 6 can have this feature if its status changed. Any pin configured as output or P60 pin configured as /INT is excluded from this function. The Port 6 input status changed interrupt can wake up the EM78P156E from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP. When waking up, the controller will continue to execute the succesive address if the global interrupt is disabled or branch to the interrupt vector 008H if the global interrupt is enabled. RF is the interrupt status register, which records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction will be fetched from address
* This specification is subject to be changed without notice.
B3-16
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EM78P156E
008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF. Refer to Fig.10. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (when enabled), the next instruction will be fetched from address 001H
VCC
DR Q
/IRQn RF
P
CLK CQ L
RPRD
IRQn . . IRQm ENI/DISI
/INT
QP D R CLK QC L
/RESET IOCF IOCFWR
IOD
IOCFRD
RFWR
Fig. 10 Interrupt input circuit VI.7 Oscillator 1. Oscillator Modes EM78P156E can be operated in four different oscillator modes. There are Internal Capacitor oscillator mode (IRC), External RC oscillator mode (ERC), High XTAL oscillator mode (HXT) and Low XTAL oscillator mode (LXT). Users can select one of them by programming MS and HLF in the CODE option register. Table 6 depicts how these four modes to be defined. The up-limited operation frequency of crystal/resonator on the different VDDs is listed in Table 7. Table 6 Oscillator Modes defined by MS, HLF, HLP and IRCEN Mode MS External RC oscillator mode 0 High XTAL oscillator mode 1 Low XTAL oscillator mode 1 Internal C, External R oscillator mode 0
HLF *X 1 0 *X
HLP *X *X 0 *X
IRCEN 1 *X *X 0
1. X, Do not care 2. The transient point of system frequency between HXT and LXY is around 400 KHz.
* This specification is subject to be changed without notice.
B3-17
8.11.1999
EM78P156E
Table 7 The summary of maximum operating speeds Conditions VDD (V) 2.5 Two clocks 3 5 6.4 2.5 Four clocks 3 5 6.5
Fxt max. (MHz) 8 12 18 20 16 24 36 40
2. Crystal Oscillator/Ceramic Resonators (XTAL) EM78P156E can be driven by an external clock signal through the OSCI pin as shown in Fig.11
OSCI OSCO EM78P156E
Ext. Clock
Fig. 11 Circuit for External Clock Input In the most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig.12 depicts the circuit. It is the same no matter in the HXT mode or in the LXT mode. Table 8 recommends the values of C1 and C2. Since each resonator has its own attribute, users should refer to their specifications for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode
C1 OSCI
EM78P156E
XTAL RS C2
OSCO
Fig. 12 Circuit for Crystal/Resonator
* This specification is subject to be changed without notice.
B3-18
8.11.1999
EM78P156E
Table 8 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Frequency Mode Frequency 455 KHz 1.00 MHz 2.0 MHz 4.0 MHz 32.768 KHz 100 KHz 200 KHz 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz C1 (pF) 100~150 40~80 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 100~150 40~80 20~40 10~30 15 25 25 20~150 15~30 15 15
Ceramic Resonator
HXT
LXT Crystal Oscillator HXT
3.
ERC Oscillator Mode For some applications whose timing need not be calculated precisely, the RC oscillator (Fig.13) offers a lot of cost savings. Nevertheless, it should be aware that the frequency of the RC oscillator is the function of the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even the operation temperature. Moreover to this, the frequency also changes slightly from one chip to another due to the process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF as well as the value of Rext should not be greater than 1M ohm. If they can not be kept in this range, the frequency is affected easily by noise, humidity and leakage. The smaller Rext the RC oscillator has, the faster frequency it gets. On the contrary, for very low Rext values, for instance, 1K, the oscillator becomes unstable because the NMOS can not discharge the current of the capacitance correctly. On a basis of the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types and the ways of PCB layout will effect the system frequency.
VCC Rext
OSCI
EM78P156E
Cext
Fig. 13 Circuit for External RC Oscillator Mode
* This specification is subject to be changed without notice.
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8.11.1999
EM78P156E
Table 9 RC Oscillator Frequencies Cext 20pF Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k Average Fosc @ 5V, 25C 3.92 MHz 2.67 MHz 1.39 MHz 1.49 KHz 1.39 MHz 940 KHz 480 KHz 52 KHz 595 KHz 400 KHz 200 KHz 21 KHz Average Fosc @ 3V, 25C 3.65 MHz 2.60 MHz 1.40 MHz 156 KHz 1.33 MHz 920 KHz 475 KHz 50 KHz 560 KHz 390 KHz 200 KHz 20 KHz
100pF
300pF
* 1. Measured on DIP packages. 2. Design reference only 4. IRC Oscillator Mode In IRC mode, it consists of an internal C which default frequency value is 4MHz. We suggest that the external Resistant value here should be 50K connected to vdd with internal C. VI.8 CODE Option Register 1. Code Option Register The EM78P156E has one Code option register which is not a part of the normal program memory. The option bits can not be accessed during normal program execution. 12 MS 11 ENWDTB 10 CLKS 9 PTB 8 HLF 7 IRCEN 6 HLP 5~0 ------
Bit 12 (MS): Oscillator type selection. 0: RC type 1: XTAL type (XTAL1 and XTAL2) Bit 11 (ENWDTB): Watchdog Timer enable. 0: Enable 1: Disable Bit 10 (CLKS): Instruction period option. 0: two oscillator periods 1: four oscillator periods Refer to the section of Instruction Set. Bit 9 (PTB): Protect bit 0: Enable 1: Disable Bit 8 (HLF): XTAL frequency selection. 0: XTAL2 type (Low frequency, 32.768KHz)
* This specification is subject to be changed without notice.
B3-20
8.11.1999
EM78P156E
1: XTAL1 type (High frequency) This bit will affect system oscillation only when Bit 12 (MS) is "1". When MS is "0", HLF must be "0". Bit 7 (IRCEN): RC oscillator selection. 0: R connected to Vdd with internal C. 1: External RC Bit 6 (HLP): Power selection. 0: Low power 1: High power Bits 5 ~ 0: Not used. 2. User's ID Register The EM78P156E has one User's ID register which is not a part of the normal program memory. The User's ID bits can not be accessed during normal program execution. 12 ~0 XXXXXXXXXXXXX Bit 12 ~ 0: User's ID code. VI.9 Power-on Considerations Any microcontroller is not warranted to start proper operation before the power supply stays in its steady state. EM78P156E is equipped with Power On Voltage Detector (POVD) which the detective level is about 1.8V. It will work well if Vdd rises quickly enough (50ms or less). In many critical applications; however, extra devices are still required to assist in solving power-up problems. VI.10 External Power-on Reset Circuit The circuit shown in Fig.14 implements an external RC to produce the reset pulse. The pulse width (time constant) should keep long enough until Vdd has reached minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40K. In this way, the voltage in pin /RESET will be held below 0.2V. The diode (D) acts a short circuit at the moment of power-down. The capacitor, C, will be discharged rapidly and fully. Rin, the current-limited resistor, protects against a high discharging current or ESD (electrostatic discharge) flowing to pin /RESET.
VDD /RESET
EM78P156E
R
D
Rin
C
Fig. 14 External Power-up Reset Circuit
* This specification is subject to be changed without notice.
B3-21
8.11.1999
EM78P156E
VI.11 Residue Voltage Protection In some applications, replacing battery as an instance, device power (Vdd) is taken off and recovered within a few seconds. A residue voltage, which trips below Vdd min but not to zero, may exist. This condition may cause a poor power-on reset. Fig.15 and Fig.16 show how to build the residue voltage protection circuit
VDD
EM78P156E
VDD Q1 10K 100K IN4684 33K
/RESET
Fig. 15 Circuit 1 for the residue voltage protection
VDD
EM78P156E
VDD Q1 R1
/RESET R3 R2
Fig. 16 Circuit 2 for the residue voltage protection
* This specification is subject to be changed without notice.
B3-22
8.11.1999
EM78P156E
VI.12 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ......). In this case, the execution takes two instruction cycles. Under some conditions, if the specification of the instruction cycle is not suitable for some applications, they can be modified as follows: (A) one instruction cycle consists of 4 oscillator periods. (B) "JMP", "CALL", "RET", "RETL", "RETI", and the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") tested to be true are executed within two instruction cycles. The instructions that write to the program counter also take two instruction cycles. The Case (A) is selected by the CODE option bit, called CLKS. One instruction cycle consists of two oscillator clocks if CLKS is low, and consists of four oscillator clocks if CLKS is high. Note that once 4 oscillator periods within one instruction cycle is selected in Case (A), the internal clock source to TCC is CLK=Fosc/4 instead of Fosc/ 2 that is shown in Fig.5. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared or tested directly. (2) The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator which specifies which one of the registers (including operational registers and general-purpose registers) to be utilized by the instruction. The symbol "b" represents a bit field designator which selects the number of the bit located in the register "R" affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value.
* This specification is subject to be changed without notice.
B3-23
8.11.1999
EM78P156E
Table 10 The list of the instruction set of EM78P156E INSTRUCTION BINARY 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 0100 rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A, SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero
8.11.1999
STATUS AFFECTED None C None T,P T,P None None None None None None None None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None None
0110 01rr rrrr 0110 10rr rrrr 0110 11rr rrrr 0111 00rr rrrr 0111 01rr rrrr 0111 10rr rrrr 0111 11rr rrrr
* This specification is subject to be changed without notice.
B3-24
EM78P156E
INSTRUCTION BINARY 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1111 kkkk kkkk HEX 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk MNEMONIC BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k OPERATION 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 001H PC k+A A STATUS AFFECTED None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
This instruction can operate on IOC5~IOC6, IOCA~IOCF only. This instruction is not recommended to operate on RF. This instruction cannot operate on RF.
* This specification is subject to be changed without notice.
B3-25
8.11.1999
EM78P156E
VII. ABSOLUTE MAXIMUM RATINGS
Items Temperature under bias Storage temperature Input voltage Output voltage Sym. TOPR TSTR VIN VO Condition Rating 0C to 70C -65C to 150C -0.3V to +6.0V -0.3V to +6.0V
VIII. DC ELECTRICAL CHARACTERISTIC (Ta=0C ~ 70C, VDD=5.0V5%, VSS=0V)
Parameter Sym. XTAL : VDD to 3V Fxt XTAL : VDD to 5V Fxt ERC : VDD to 5V FRC IRC : VDD to 5V FRC Input Leakage Current IIL for input pins Input High Voltage VIH Input Low Voltage VIL Input High Threshold Voltage VIHT Input Low Threshold Voltage VILT Clock Input High Voltage VIHX Clock Input Low Voltage VILX Output High Voltage VOH1 (Port 5,6) Output Low Voltage VOL1 (P50~P53,P62~P67) Output Low Voltage VOL2 (P60,P61) Pull-high current IPH Pull-down current IPD Power-down current ISB1 Power-down current Operating supply current (VDD=3V) at two cycles/two clocks Operating supply current (VDD=3V) at two cycles/two clocks Operating supply current (VDD=5V) at two cycles/two clocks Operating supply current (VDD=5V) at two cycles/two clocks ICC4 ICC3 ISB2 ICC1 Condition Two cycles with two clocks R : 5.1K , C : 100pF R : 50K VIN = VDD, VSS Ports 5, 6 Ports 5, 6 /RESET, TCC /RESET, TCC OSCI OSCI IOH = -12mA IOL = 10.5mA IOL = 12mA Pull-high active, input pin at VSS Pull-down active, input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled /RESET='High', Fosc=32KHz(Crystal type, CLKS="0"), output pin floating, WDT disabled /RESET='High', Fosc=32KHz(Crystal type,CLKS="0"), output pin floating, WDT enabled /RESET='High', Fosc=4MHz (Crystal type,CLKS="0"), output pin floating WDT enable /RESET='High', Fosc=10MHz (Crystal type,CLKS="0"), output pin floating WDT enable 4
8.11.1999
Min. DC DC F20% F20%
Typ.
760 4
Max. 12.0 18.0 F20% F20% 1
Unit MHz MHz KHz MHz A V V V V V V V V V A A A A A
2.0 0.8 2.0 0.8 3.5 1.5 2.4 0.4 0.4 -50 25 -70 50 -240 120 1 10
15
15
30
ICC2
20
35
A
1.6
mA
mA
* This specification is subject to be changed without notice.
B3-26
EM78P156E
IX. VOLTAGE DETECTOR ELECTRICAL CHARACTERISTIC (Ta = 25C)
Parameter Detect voltage Release voltage Current consumption Operating voltage Temperature characteristic of Vdet Symbol Vdet Vrel Iss Vop Vdet/ Ta 0C Ta 70C VDD = 5V 0.7* Condition Min. 1.7 Typ. 1.8 Vdet x1.05 5 5.5 -2 Max. 1.9 Unit V V A V mV/C
X.
AC ELECTRICAL CHARACTERISTICS (Ta=0C ~ 70C, VDD=5.0V5%, VSS=0V)
Parameter Symbol Dclk Tins Ttcc Tdrh Twdt Tset Thold Tdelay XTAL Type RC Type Ta = 25C Ta = 25C Condition Min. 45 125 500 (Tins+20)/N* 16.8 16.8 0 20 50 Typ. 50 Max. 55 DC DC Unit % ns ns ns ms ms ns ns ns
Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time Watchdog Timer period Input pin setup time Input pin hold time Output pin delay time
Cload=20pF
Note : N*= selected prescaler ratio.
* This specification is subject to be changed without notice.
B3-27
8.11.1999
EM78P156E
XI. TIMING DIAGRAMS
AC Test Input/Output Waveform
2.4 2.0 0.8 0.45 TEST PONITS 0.8 2.0
AC Testing : Input is driven at 2.4V for logic "1", and 0.45V for logic "0". Timing measurements are made at 2.0V for logic "1", and 0.8V for logic "0". RESET Timing (CLK="0")
NOP Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLK="0")
Tins
CLK
TCC
Ttcc
* This specification is subject to be changed without notice.
B3-28
8.11.1999

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